A Scalable Digital Architecture of a Kohonen Neural Network

Kohonen self-organizing feature maps are unsupervised learning neural networks that categorize or classify data. Efficient hardware implementation of such neural networks requires the definition of a certain number of simplifications to the original algorithm. In particular, multiplications should be avoided by means of simplifications in the distance metric, the neighborhood function and the learning parameter values. In many applications, a scalable solution becomes necessary due to the limited memory resources available in many embedded platforms. In this paper, a scalable Kohonen map called Local Winner-TakeAll (LWTA) design with Minkowski norm L∞ and an exponential neighboring function is defined, and its hardware architecture is presented. The scalability of the net is achieved via a Local Winner –TakeAll approach. Results of VHDL simulations as well as synthesis on an FPGA of the proposed architecture demonstrate satisfactory functionality of such architecture.